// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  system_counter_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2015/11/15
// Description   :  The description of Totem
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 11:44:20 Create file
// ******************************************************************************

#ifndef __SYSTEM_COUNTER_REG_OFFSET_FIELD_H__
#define __SYSTEM_COUNTER_REG_OFFSET_FIELD_H__

#define SYSTEM_COUNTER_HDBG_LEN    1
#define SYSTEM_COUNTER_HDBG_OFFSET 1
#define SYSTEM_COUNTER_EN_LEN      1
#define SYSTEM_COUNTER_EN_OFFSET   0

#define SYSTEM_COUNTER_DBGH_LEN    1
#define SYSTEM_COUNTER_DBGH_OFFSET 1

#define SYSTEM_COUNTER_CNTCVL_L_32_LEN    32
#define SYSTEM_COUNTER_CNTCVL_L_32_OFFSET 0

#define SYSTEM_COUNTER_CNTCVU_U_32_LEN    32
#define SYSTEM_COUNTER_CNTCVU_U_32_OFFSET 0

#define SYSTEM_COUNTER_FREQ_LEN    32
#define SYSTEM_COUNTER_FREQ_OFFSET 0

#define SYSTEM_COUNTER_SIZE_LEN     4
#define SYSTEM_COUNTER_SIZE_OFFSET  4
#define SYSTEM_COUNTER_DES_2_LEN    4
#define SYSTEM_COUNTER_DES_2_OFFSET 0







#define SYSTEM_COUNTER_PART_0_LEN    8
#define SYSTEM_COUNTER_PART_0_OFFSET 0

#define SYSTEM_COUNTER_DES_0_LEN     4
#define SYSTEM_COUNTER_DES_0_OFFSET  4
#define SYSTEM_COUNTER_PART_1_LEN    4
#define SYSTEM_COUNTER_PART_1_OFFSET 0

#define SYSTEM_COUNTER_REVISION_LEN    4
#define SYSTEM_COUNTER_REVISION_OFFSET 4
#define SYSTEM_COUNTER_JEDEC_LEN       1
#define SYSTEM_COUNTER_JEDEC_OFFSET    3
#define SYSTEM_COUNTER_DES_1_LEN       3
#define SYSTEM_COUNTER_DES_1_OFFSET    0

#define SYSTEM_COUNTER_REVAND_LEN    4
#define SYSTEM_COUNTER_REVAND_OFFSET 4
#define SYSTEM_COUNTER_CMOD_LEN      4
#define SYSTEM_COUNTER_CMOD_OFFSET   0

#define SYSTEM_COUNTER_PRMBL_0_LEN    8
#define SYSTEM_COUNTER_PRMBL_0_OFFSET 0

#define SYSTEM_COUNTER_CLASS_LEN      4
#define SYSTEM_COUNTER_CLASS_OFFSET   4
#define SYSTEM_COUNTER_PRMBL_1_LEN    4
#define SYSTEM_COUNTER_PRMBL_1_OFFSET 0

#define SYSTEM_COUNTER_PRMBL_2_LEN    8
#define SYSTEM_COUNTER_PRMBL_2_OFFSET 0

#define SYSTEM_COUNTER_PRMBL_3_LEN    8
#define SYSTEM_COUNTER_PRMBL_3_OFFSET 0

#define SYSTEM_COUNTER_CNTCVL_L_32_LEN    32
#define SYSTEM_COUNTER_CNTCVL_L_32_OFFSET 0

#define SYSTEM_COUNTER_CNTCVU_U_32_LEN    32
#define SYSTEM_COUNTER_CNTCVU_U_32_OFFSET 0

#define SYSTEM_COUNTER_SIZE_LEN     4
#define SYSTEM_COUNTER_SIZE_OFFSET  4
#define SYSTEM_COUNTER_DES_2_LEN    4
#define SYSTEM_COUNTER_DES_2_OFFSET 0







#define SYSTEM_COUNTER_PART_0_LEN    8
#define SYSTEM_COUNTER_PART_0_OFFSET 0

#define SYSTEM_COUNTER_DES_0_LEN     4
#define SYSTEM_COUNTER_DES_0_OFFSET  4
#define SYSTEM_COUNTER_PART_1_LEN    4
#define SYSTEM_COUNTER_PART_1_OFFSET 0

#define SYSTEM_COUNTER_REVISION_LEN    4
#define SYSTEM_COUNTER_REVISION_OFFSET 4
#define SYSTEM_COUNTER_JEDEC_LEN       1
#define SYSTEM_COUNTER_JEDEC_OFFSET    3
#define SYSTEM_COUNTER_DES_1_LEN       3
#define SYSTEM_COUNTER_DES_1_OFFSET    0

#define SYSTEM_COUNTER_REVAND_LEN    4
#define SYSTEM_COUNTER_REVAND_OFFSET 4
#define SYSTEM_COUNTER_CMOD_LEN      4
#define SYSTEM_COUNTER_CMOD_OFFSET   0

#define SYSTEM_COUNTER_PRMBL_0_LEN    8
#define SYSTEM_COUNTER_PRMBL_0_OFFSET 0

#define SYSTEM_COUNTER_CLASS_LEN      4
#define SYSTEM_COUNTER_CLASS_OFFSET   4
#define SYSTEM_COUNTER_PRMBL_1_LEN    4
#define SYSTEM_COUNTER_PRMBL_1_OFFSET 0

#define SYSTEM_COUNTER_PRMBL_2_LEN    8
#define SYSTEM_COUNTER_PRMBL_2_OFFSET 0

#define SYSTEM_COUNTER_PRMBL_3_LEN    8
#define SYSTEM_COUNTER_PRMBL_3_OFFSET 0

#endif // __SYSTEM_COUNTER_REG_OFFSET_FIELD_H__
